This invention relates generally to static random access memory (SRAM) cells and particularly to SRAM cells which utilize gated diode load elements.
Presently, using complementary metal oxide silicon (CMOS) technology, SRAM cells are constructed using either a four transistor or a six transistor implementation. Typically, the four transistor configuration uses a polysilicon load element which functions as a passive resistor. See, for example, T. Ohzone, T. Hirao, K. Tsuji, S. Horiuchi, and S. Takayanagi, A 2K.times.8-Bit Static MOS RAM with a New Memory Cell Structure, IEEE J. Solid-State Circuits, vol. SC-15, April 1980, pp. 201-205. The six transistor configuration typically uses p-channel transistors as active load elements. The p-channel transistors used as active load elements may be conventional transistors or thin film transistors. The thin film transistors are built in silicon film deposited over the memory cell, similar to a polysilicon load resistor. See for example, N. Okazaki, T. Komatsu, N. Hoshi, K. Tsuboi and T. Shimada, A 16 ns 2K.times.8 Bit Full CMOS SRAM, IEEE Journal of Solid-State Circuits, Volume SC-10, No. 5, October 1984, pp. 552-556.
The four transistor configuration has the advantage of a smaller size. The four transistor configuration has the disadvantage of requiring a more complex process which is not easily implemented in application specific integrated circuit (ASIC) processes (or process flows). The four transistor configuration also has the disadvantage that it results in higher standby currents.
The six transistor configuration has the advantage that it can be implemented in the standard ASIC CMOS process. However, SRAM cells which utilize the six transistor configuration are larger than SRAM cells which utilize the four transistor configuration and are more susceptible to latch up. Latch up occurs when the four-layer NPNP CMOS structure acts like a silicon controlled rectifier (SCR) and switches from a high impedance state to a low impedance state in response to a triggering signal. This latch up is detrimental and sometimes destructive to the integrated circuit.